The present invention relates to an electronic data storage and recovery system, and more particularly to a system for locking a clock onto the frequency of data recorded on a storage medium and tracking or rejecting any frequency variation on the media.
There is a continual desire in the electronic data storage industry to increase the amount of data that can be stored in a given form factor. In order to store a greater amount of data either the density of data storage must be increased or a better use of disk format must be achieved. Increased format efficiency can be achieved by reducing the amount of inter-sector gap (space between adjacent data sectors or space between data sectors and servo wedges). Traditionally, the inter-sector gap space was left on the media to allow for changes in rotational frequency over the life of the product. Typical rotational frequency changes come in the form of non-ideal disk eccentricity, disk slips, or mechanical shocks. Traditional systems do not modulate clocks to account for rotational frequency changes but instead employ a traditional clock recovery scheme, such as circuit 10 shown in FIG. 1.
PLL circuit 10 includes reference clock signal 12, generated by a crystal oscillator, for example, that is input to servo synthesizer/PLL 14 and read synthesizer/PLL 16. Servo synthesizer/PLL 14 receives reference clock signal 12 and is programmed to the nominal servo bit rate. Read synthesizer/PLL 16 receives reference clock signal 12 and is programmed to the nominal read bit rate. Servo synthesizer/PLL 14 produces servo clock signal 18, and read synthesizer/PLL 16 produces a read clock signal. Servo clock signal 18 and the read clock signal are multiplexed together by multiplexer 20, and mixer 22 operates to produce recovered clock signal 24. Digital phase locked loop (DPLL) circuit 26 receives recovered clock signal 24 and incoming data phase error signal 27 to modify mixer 22 to lock onto the incoming servo and read data.
PLL circuits such as circuit 10 shown in FIG. 1 have proved to be excellent circuits for maintaining an accurate data clock in current systems. For better format efficiencies with the written media and to decrease the amount of inter-sector gap required on the media, a system can no longer ignore the rotational frequency variations of the media. It is therefore necessary for a clock circuit with highly accurate “sub-T” error measurement resolution (within a fraction of a clock cycle, where T is a clock cycle period) to be developed for these systems. This allows tracking or rejecting of the rotational frequency variations of the media.